1. Technical Field
The present invention relates to semiconductor memory apparatus, and more particularly, to an apparatus and a method of generating a power-up signal of a semiconductor memory apparatus.
2. Related Art
In a semiconductor memory apparatus, a power-up signal is a signal that indicates, when an external power supply Vext is supplied at the beginning of an operation, that the level of the power supply has reached a level required for normal operation of the memory. When the power supply does not reach the level for normal operation of the memory, that is, when the power supply is used before the level of the power supply reaches the level for normal operation of the memory, the semiconductor memory apparatus may operate abnormally. When the power-up signal is activated, the power-up signal may be in a high level or a low level. Hereinafter, it is assumed that the power-up signal is in the high-level.
Accordingly, the semiconductor memory apparatus essentially includes a power-up signal generator that generates the power-up signal and supplies the generated power-up signal to individual constituent elements for the operation of the semiconductor memory apparatus.
Hereinafter, an apparatus for generating a power-up signal of a semiconductor memory according to the related art will be described with reference to the accompanying drawings.
As shown in FIG. 1, an apparatus for generating a power-up signal of a semiconductor memory apparatus according to the related art includes a resistor array that includes resistors R1 to R4 and is connected between a power supply terminal Vext and a ground terminal, a first transistor array that includes transistors P1 to P3 and whose one end is connected to the power supply terminal Vext, a second transistor array that includes transistors N1 to N3, and whose one end is connected to the other end of the first transistor array and whose other end is connected to the ground terminal, and inverters 11 to 13 connected to a connection node A between the first transistor array P1 to P3 and the second transistor array N1 to N3.
All gates of the transistors P1 to P3 of the first transistor array are commonly connected to the ground terminal. Further, an intermediate node of the resistor array R1 to R4 is connected commonly to all gates of the transistors N1 to N3 of the second transistor array.
The operation of the related art having the above-described configuration will be described.
First, the transistors P1 to P3 of the first transistor array are P-type transistors and are in the ON state since the gates of the individual transistors are connected to the ground terminal when the power supply is initially applied. The N-type transistors N1 to N3 of the second transistor array are in the OFF state since the power supply voltage level is rising. Accordingly, the node A that is in the high level is changed to the low level by the inverters 11 to 13. Therefore, the power-up signal is in an inactivation state.
Meanwhile, the power supply is divided by the resistor array having the resistors R1 to R4. The divided power supply is supplied to the gates of all the transistors N1 to N3 of the second transistor array. Then, as the power supply voltage rises, all the transistors N1 to N3 of the second transistor array are changed from the OFF state to the ON state, and the node A is changed to the low level. Accordingly, the low level of the node A is output as the high level through the inverters 11 to 13, and thus the power-up signal is activated.
That is, the level of the node A is changed according to a size ratio between the first transistor array having the transistors P1 to P3 and the second transistor array having the transistors N1 to N3, and a threshold voltage of each of the transistors N1 to N3 of the second transistor array. Thus activation of the power-up signal is determined.
However, according to the related art, since the configuration for generating a power-up signal is determined by the ratios of the resistors and the transistors, there is a problem in that the power-up signal cannot be generated or cannot be normally generated due to variations in conditions, such as temperature or transistor characteristics.